{"id":785,"date":"2021-02-09T12:34:39","date_gmt":"2021-02-09T04:34:39","guid":{"rendered":"http:\/\/47.91.14.247\/?page_id=785"},"modified":"2021-02-09T12:37:06","modified_gmt":"2021-02-09T04:37:06","slug":"zynq","status":"publish","type":"page","link":"https:\/\/www.zkey-tech.com\/index.php\/zynq\/","title":{"rendered":"Zynq 7"},"content":{"rendered":"<p>[vc_row full_width=&#8221;stretch_row&#8221; parallax=&#8221;content-moving&#8221; parallax_image=&#8221;56&#8243; css=&#8221;.vc_custom_1506680193286{padding-top: 128px !important;padding-bottom: 128px !important;}&#8221;][vc_column][vc_custom_heading text=&#8221;Zynq 7&#8243; font_container=&#8221;tag:h1|text_align:center|color:%23ffffff&#8221; use_theme_fonts=&#8221;yes&#8221; css=&#8221;.vc_custom_1612845422270{margin-bottom: 0px !important;}&#8221;][\/vc_column][\/vc_row][vc_row css=&#8221;.vc_custom_1506680283788{padding-top: 30px !important;padding-bottom: 12px !important;}&#8221;][vc_column width=&#8221;2\/3&#8243;][vc_column_text]<b>FPGA FMC Carrier, Xilinx Zynq-7000, 3U VPX<\/b><\/p>\n<ul>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">3U FPGA carrier for FPGA Mezzanine Card (FMC) per VITA 46 and VITA 57<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Xilinx Zynq-7000 FPGA in FFG-900 package (XC7Z100 or XC7Z045)<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">High-performance clock jitter cleaner<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Protocols such as PCIe, SRIO, 10GbE\/40Gbe, etc. are FPGA programmable<\/span><\/li>\n<\/ul>\n<p><span style=\"font-weight: 400;\">The VPX_Z7CB100T-2C is a FPGA Carrier (VITA 46) with an FMC (VITA 57) interface. The unit has an onboard, re-configurable FPGA which interfaces directly to the FMC DP0-9 and all FMC LA\/HA\/HB pairs. The FPGA has two sets of one GB DDR3 memory (32-bit wide). This allows for large buffer sizes to be stored during processing as well as for queuing the data to the host. The FPGA package includes an integrated SoC processor. The processor has a separate single bank of DDR3 (32-bit wide). The module supports dual GbE and, dependent on FPGA code loaded, PCIe up to Gen3 (dual x4 or x8 lane), or dual SRIO, 10GbE or 40GbE on P1. There are 16 single ended lanes routed from the FPGA to P2.<\/span>[\/vc_column_text][\/vc_column][vc_column width=&#8221;1\/3&#8243;][vc_single_image image=&#8221;786&#8243; img_size=&#8221;medium&#8221;][\/vc_column][\/vc_row][vc_row][vc_column][vc_column_text]<\/p>\n<table>\n<tbody>\n<tr>\n<td colspan=\"2\"><span style=\"font-weight: 400;\">Power Connection<\/span><\/td>\n<\/tr>\n<tr>\n<td><span style=\"font-weight: 400;\">Connector<\/span><\/td>\n<td><span style=\"font-weight: 400;\">VPX P0<\/span><\/td>\n<\/tr>\n<tr>\n<td><span style=\"font-weight: 400;\">Supply Voltage<\/span><\/td>\n<td><span style=\"font-weight: 400;\">Single DC12V<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"2\"><span style=\"font-weight: 400;\">Environment Condition<\/span><\/td>\n<\/tr>\n<tr>\n<td><span style=\"font-weight: 400;\">Operating Temperature<\/span><\/td>\n<td><span style=\"font-weight: 400;\">-0 <\/span><span style=\"font-weight: 400;\">\u2103 <\/span><span style=\"font-weight: 400;\">~ +60 <\/span><span style=\"font-weight: 400;\">\u2103<\/span><\/td>\n<\/tr>\n<tr>\n<td><span style=\"font-weight: 400;\">Storage Temperature<\/span><\/td>\n<td><span style=\"font-weight: 400;\">-40 <\/span><span style=\"font-weight: 400;\">\u2103 <\/span><span style=\"font-weight: 400;\">~ +85 <\/span><span style=\"font-weight: 400;\">\u2103<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>[\/vc_column_text][\/vc_column][\/vc_row]<\/p>\n","protected":false},"excerpt":{"rendered":"<p>[vc_row full_width=&#8221;stretch_row&#8221; parallax=&#038; [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-785","page","type-page","status-publish","hentry"],"jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/www.zkey-tech.com\/index.php\/wp-json\/wp\/v2\/pages\/785","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.zkey-tech.com\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.zkey-tech.com\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.zkey-tech.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.zkey-tech.com\/index.php\/wp-json\/wp\/v2\/comments?post=785"}],"version-history":[{"count":3,"href":"https:\/\/www.zkey-tech.com\/index.php\/wp-json\/wp\/v2\/pages\/785\/revisions"}],"predecessor-version":[{"id":789,"href":"https:\/\/www.zkey-tech.com\/index.php\/wp-json\/wp\/v2\/pages\/785\/revisions\/789"}],"wp:attachment":[{"href":"https:\/\/www.zkey-tech.com\/index.php\/wp-json\/wp\/v2\/media?parent=785"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}